[SpinalHDL] FPGA に JTAG 機能を載せて Python から制御する

package flogics.lib.pwm

import spinal.core._
import spinal.lib._
import spinal.lib.Counter

class Pwm(size: Int) extends Component {
  val io = new Bundle {
    val width = in UInt (size bits)
    val output = out Bool
  }

  val ct = Counter(size bits)

  ct.increment()
  io.output := ct.value < io.width
}

import spinal.core._
import spinal.lib._
import spinal.lib.com.jtag.{Jtag, JtagTap}
import flogics.lib.pwm._

class JtagPwm_TinyFPGA_BX extends Component {
  val io = new Bundle {
    val CLK = in Bool
    val PWM = out Bool
    val TCK = in Bool
    val TDI = in Bool
    val TDO = out Bool
    val TMS = in Bool
    val USBPU = out Bool
  }

  val pwm_size = 8

  val core_clock_domain = ClockDomain(
    clock = io.CLK,
    frequency = FixedFrequency(16 MHz),
    config = ClockDomainConfig(
      resetKind = BOOT
    )
  )

  class MyJtagTap extends Component {
    val io = new Bundle {
      val jtag = slave(Jtag())
      val width = out UInt(pwm_size bits)
      val pwm = in Bool
    }

    val pwm_reg = RegNext(io.pwm).addTag(crossClockDomain)

    val tap = new JtagTap(io.jtag, 8)
    val idcodeArea = tap.idcode(B"x87654321")(instructionId = 4)
    val widthArea = tap.write(io.width)(instructionId = 5)
    val pwmArea = tap.read(pwm_reg)(instructionId = 6)
  }

  val jtag_area = new ClockingArea(ClockDomain(io.TCK)) {
    val jtag = new MyJtagTap()
    jtag.io.jtag.tms <> io.TMS
    jtag.io.jtag.tdi <> io.TDI
    jtag.io.jtag.tdo <> io.TDO
  }

  val core_area = new ClockingArea(core_clock_domain) {
    io.USBPU := False

    val pwm = new Pwm(
      size = pwm_size
    )
    pwm.io.width := jtag_area.jtag.io.width
    jtag_area.jtag.io.pwm := pwm.io.output
    io.PWM := pwm.io.output
  }
}

object JtagPwm_TinyFPGA_BX {
  def main(args: Array[String]): Unit = {
    SpinalVerilog(new JtagPwm_TinyFPGA_BX)
  }
}

    val tap = new JtagTap(io.jtag, 8)
    val idcodeArea = tap.idcode(B"x87654321")(instructionId = 4)
    val widthArea = tap.write(io.width)(instructionId = 5)
    val pwmArea = tap.read(pwm_reg)(instructionId = 6)

from pyftdi.jtag import JtagEngine
from pyftdi.bits import BitSequence
import time

FTDI_BOARD = 'ftdi://ftdi:232h/1'
SPEED = 5
TCK_FREQ = 1e6
MAX_WIDTH = 255

def read_pwm():
    jtag.write_ir(RD_PWM)
    pwm = jtag.read_dr(1)
    print("PWM: 0x%x" % int(pwm))

# Define Instructions
IDCODE = BitSequence('00000100', msb=True, length=8)
WR_WIDTH = BitSequence('00000101', msb=True, length=8)
RD_PWM = BitSequence('00000110', msb=True, length=8)

# Initialize
jtag = JtagEngine(frequency=TCK_FREQ)
jtag.configure(FTDI_BOARD)

jtag.reset()    # Test Logic Reset (5 times of TMS=1)

# To Shift-IR, Exit1-IR and finally move to UpdateIR
jtag.write_ir(IDCODE)

# Move to Shift-DR, repeat Shift-DR, wait 15ms, and move to Test-Logic Reset
idcode = jtag.read_dr(32)
print("IDCODE (reset): 0x%x" % int(idcode))

width = 0
dir = 1
while True:
    jtag.write_ir(WR_WIDTH)
    jtag.write_dr(BitSequence(width, msb=False, length=8))

    width += dir * SPEED
    if width >= MAX_WIDTH:
        read_pwm()
        dir = -1
        width = MAX_WIDTH
    elif width <= 0:
        read_pwm()
        dir = 1
        width = 0

    time.sleep(0.001)